7.8

CVE-2026-23554

Use after free of paging structures in EPT

The Intel EPT paging code uses an optimization to defer flushing of any cached
EPT state until the p2m lock is dropped, so that multiple modifications done
under the same locked region only issue a single flush.

Freeing of paging structures however is not deferred until the flushing is
done, and can result in freed pages transiently being present in cached state.
Such stale entries can point to memory ranges not owned by the guest, thus
allowing access to unintended memory regions.
Daten sind bereitgestellt durch National Vulnerability Database (NVD)
Xen ≫ Xen HwPlatformx86 Version >= 4.17
VulnDex Vulnerability Enrichment
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EPSS Metriken
Typ Quelle Score Percentile
EPSS FIRST.org 0.01% 0.025
CVSS Metriken
Quelle Base Score Exploit Score Impact Score Vector String
134c704f-9b21-4f2e-91b3-4a467353bcc0 7.8 1.1 6
CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:H/A:H
CWE-367 Time-of-check Time-of-use (TOCTOU) Race Condition

The product checks the state of a resource before using that resource, but the resource's state can change between the check and the use in a way that invalidates the results of the check. This can cause the product to perform invalid actions when the resource is in an unexpected state.

http://www.openwall.com/lists/oss-security/2026/03/17/6
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