CVE-2021-26376
- EPSS 0.12%
- Published 11.05.2022 17:15:08
- Last modified 21.11.2024 05:56:15
Insufficient checks in System Management Unit (SMU) FeatureConfig may result in reenabling features potentially resulting in denial of resources and/or denial of service.
CVE-2021-26375
- EPSS 0.08%
- Published 11.05.2022 17:15:08
- Last modified 21.11.2024 05:56:14
Insufficient General Purpose IO (GPIO) bounds check in System Management Unit (SMU) may result in access/updates from/to invalid address space that could result in denial of service.
CVE-2021-26373
- EPSS 0.12%
- Published 11.05.2022 17:15:08
- Last modified 21.11.2024 05:56:14
Insufficient bound checks in the System Management Unit (SMU) may result in a system voltage malfunction that could result in denial of resources and/or possibly denial of service.
CVE-2021-26339
- EPSS 0.09%
- Published 11.05.2022 17:15:08
- Last modified 21.11.2024 05:56:08
A bug in AMD CPU’s core logic may allow for an attacker, using specific code from an unprivileged VM, to trigger a CPU core hang resulting in a potential denial of service. AMD believes the specific code includes a specific x86 instruction sequence t...
CVE-2021-26401
- EPSS 0.13%
- Published 11.03.2022 18:15:11
- Last modified 21.11.2024 05:56:18
LFENCE/JMP (mitigation V2-2) may not sufficiently mitigate CVE-2017-5715 on some AMD CPUs.
CVE-2021-26341
- EPSS 0.08%
- Published 11.03.2022 18:15:10
- Last modified 21.11.2024 05:56:09
Some AMD CPUs may transiently execute beyond unconditional direct branches, which may potentially result in data leakage.
CVE-2021-26336
- EPSS 0.13%
- Published 16.11.2021 19:15:08
- Last modified 21.11.2024 05:56:08
Insufficient bounds checking in System Management Unit (SMU) may cause invalid memory accesses/updates that could result in SMU hang and subsequent failure to service any further requests from other components.
CVE-2021-26337
- EPSS 0.13%
- Published 16.11.2021 19:15:08
- Last modified 21.11.2024 05:56:08
Insufficient DRAM address validation in System Management Unit (SMU) may result in a DMA read from invalid DRAM address to SRAM resulting in SMU not servicing further requests.