Amd

Ryzen 5600x Firmware

17 vulnerabilities found.

Hinweis: Diese Liste kann unvollständig sein. Daten werden ohne Gewähr im Ursprungsformat bereitgestellt.
  • EPSS 0.16%
  • Published 09.05.2023 19:15:10
  • Last modified 28.01.2025 16:15:30

Insufficient bounds checking in ASP (AMD Secure Processor) may allow for an out of bounds read in SMI (System Management Interface) mailbox checksum calculation triggering a data abort, resulting in a potential denial of service.

  • EPSS 0.07%
  • Published 15.11.2022 22:15:10
  • Last modified 30.04.2025 15:15:52

Incorrect pointer checks within the the FwBlockServiceSmm driver can allow arbitrary RAM modifications During review of the FwBlockServiceSmm driver, certain instances of SpiAccessLib could be tricked into writing 0xff to arbitrary system and SMRAM a...

  • EPSS 0.19%
  • Published 12.05.2022 19:15:48
  • Last modified 21.11.2024 05:56:15

A malicious or compromised UApp or ABL may be used by an attacker to issue a malformed system call to the Stage 2 Bootloader potentially leading to corrupt memory and code execution.

  • EPSS 0.06%
  • Published 12.05.2022 19:15:48
  • Last modified 21.11.2024 05:56:13

Insufficient check of the process type in Trusted OS (TOS) may allow an attacker with privileges to enable a lesser privileged process to unmap memory owned by a higher privileged process resulting in a denial of service.

  • EPSS 0.19%
  • Published 12.05.2022 19:15:48
  • Last modified 21.11.2024 05:56:05

Failure to verify the protocol in SMM may allow an attacker to control the protocol and modify SPI flash resulting in a potential arbitrary code execution.

  • EPSS 0.82%
  • Published 04.02.2022 23:15:10
  • Last modified 21.11.2024 05:00:35

When combined with specific software sequences, AMD CPUs may transiently execute non-canonical loads and store using only the lower 48 address bits potentially resulting in data leakage.

  • EPSS 0.13%
  • Published 16.11.2021 19:15:08
  • Last modified 21.11.2024 05:56:08

Insufficient DRAM address validation in System Management Unit (SMU) may result in a DMA read from invalid DRAM address to SRAM resulting in SMU not servicing further requests.