6.7
CVE-2025-52536
- EPSS 0.02%
- Veröffentlicht 10.02.2026 19:09:04
- Zuletzt bearbeitet 10.02.2026 21:51:48
- Quelle psirt@amd.com
- CVE-Watchlists
- Unerledigt
Improper Prevention of Lock Bit Modification in SEV firmware could allow a privileged attacker to downgrade firmware potentially resulting in a loss of integrity.
Verknüpft mit AI von unstrukturierten Daten zu bestehenden CPE der NVD
Daten sind bereitgestellt durch das CVE Programm von einer CVE Numbering Authority (CNA) (Unstrukturiert).
HerstellerAMD
≫
Produkt
AMD EPYC™ 9004 Series Processors
Default Statusaffected
Version
GenoaPI 1.0.0.G
Status
unaffected
HerstellerAMD
≫
Produkt
AMD EPYC™ 7003 Series Processors
Default Statusaffected
Version
MilanPI 1.0.0.H
Status
unaffected
HerstellerAMD
≫
Produkt
AMD EPYC™ 9005 Series Processors
Default Statusaffected
Version
TurinPI 1.0.0.5
Status
unaffected
HerstellerAMD
≫
Produkt
AMD EPYC™ 8004 Series Processors
Default Statusaffected
Version
GenoaPI 1.0.0.G
Status
unaffected
HerstellerAMD
≫
Produkt
AMD EPYC™ Embedded 7003 Series Processors
Default Statusaffected
Version
EmbMilanPI-SP3 v9 1.0.0.C
Status
unaffected
HerstellerAMD
≫
Produkt
AMD EPYC™ Embedded 9004 Series Processors (formerly codenamed "Genoa")
Default Statusaffected
Version
EmbGenoaPI-SP5 1.0.0.B
Status
unaffected
HerstellerAMD
≫
Produkt
AMD EPYC™ Embedded 9005 Series Processors
Default Statusaffected
Version
EmbTurinPI-SP5_1.0.0.1
Status
unaffected
HerstellerAMD
≫
Produkt
AMD EPYC™ Embedded 9004 Series Processors (formerly codenamed "Bergamo")
Default Statusaffected
Version
EmbGenoaPI-SP5 1.0.0.B
Status
unaffected
HerstellerAMD
≫
Produkt
AMD EPYC™ Embedded 8004 Series Processors
Default Statusaffected
Version
EmbGenoaPI-SP5 1.0.0.B
Status
unaffected
| Typ | Quelle | Score | Percentile |
|---|---|---|---|
| EPSS | FIRST.org | 0.02% | 0.039 |
| Quelle | Base Score | Exploit Score | Impact Score | Vector String |
|---|---|---|---|---|
| psirt@amd.com | 6.7 | 0 | 0 |
CVSS:4.0/AV:L/AC:L/AT:N/PR:H/UI:N/VC:N/VI:H/VA:N/SC:N/SI:N/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X
|
CWE-1231 Improper Prevention of Lock Bit Modification
The product uses a trusted lock bit for restricting access to registers, address regions, or other resources, but the product does not prevent the value of the lock bit from being modified after it has been set.