6.5
CVE-2023-28746
- EPSS 0.05%
- Veröffentlicht 14.03.2024 17:15:50
- Zuletzt bearbeitet 26.04.2025 20:15:30
- Quelle secure@intel.com
- CVE-Watchlists
- Unerledigt
Information exposure through microarchitectural state after transient execution from some register files for some Intel(R) Atom(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.
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Herstellern/a
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Produkt
Intel(R) Atom(R) Processors
Default Statusunaffected
Version
See references
Status
affected
| Typ | Quelle | Score | Percentile |
|---|---|---|---|
| EPSS | FIRST.org | 0.05% | 0.157 |
| Quelle | Base Score | Exploit Score | Impact Score | Vector String |
|---|---|---|---|---|
| secure@intel.com | 6.5 | 2 | 4 |
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N
|
CWE-1342 Information Exposure through Microarchitectural State after Transient Execution
The processor does not properly clear microarchitectural state after incorrect microcode assists or speculative execution, resulting in transient execution.